Many different types of memory cell designs exist in the art, each with its own advantages and disadvantages. For example, a dynamic random access memory (DRAM) cell comprises a capacitor and an access transistor. Such a cell design is beneficial in that it can be made very dense. However, DRAM cells are volatile, meaning the cells loose their stored data after power is removed from the device. Moreover, DRAM cells, even when powered, must be periodically refreshed to retain their data states. A static random access memory (SRAM) cell is beneficial in that it can be accessed very quickly. However, SRAM cells draw relatively large amounts of current and are not terribly dense as they typically require 4 or 6 transistors in the design of a single cell. Moreover, such cells, like DRAM cells, are also volatile. Electrically erasable programmable read only memory (EEPROM) cells, such as flash cells, are non-volatile and relatively dense and quick to read. However, such cells take time to write and erase, and are subject to wearing out after a certain number of write/erase cycles.
Thus, the art continues to search for a memory cell design that has the benefits of the previously-mentioned cells designs without their negative aspects. In this regard, Silicon (or Semiconductor)-on-insulator (SOI) technologies provide interesting alternatives. For example, in S. Okhonin et al., “A SOI Capacitor-less 1T-DRAM Concept,” 2001 IEEE International SOI Conference, 0-7803-6739-1/01 (Oct. 1, 2001), and P. Fazan et al., “Capacitor-less 1T-DRAM Concept,” 2002 IEEE International SOI Conference, pg. 10–13, 0-7803-7439-b/02 (Oct. 2, 2002), both of which are hereby incorporated by reference in their entireties, it was suggested to fabricate a DRAM cell using a single transistor. The state of the memory cell is defined by the floating body potential and thereby the associated conductance of the SOI transistor. The body potential, and hence the logic ‘1’ and ‘0’ memory states, is altered by incorporating excess holes (positive charges) or excess electrons (negative charges) in the floating body of the memory transistor. However, this cell is volatile, and moreover could suffer from reliability and hysteretic problems which would ultimately affect cell performance and memory state retention. Moreover, like a typical DRAM cell, it needs to be refreshed.
A non-volatile version of a one-transistor SOI floating-body RAM cell was also proposed in U.S. Published Patent Applications U.S. 2004/0041206 (Ser. No. 10/425,483, filed Apr. 29, 2003) and 2004/0041208 (Ser. No. 10/232,846, file Aug. 30, 2002) by the present inventor, which are hereby incorporated by reference in their entireties. In these applications, a charge trapping layer is added underneath the access transistor to provide a material on which charge can be stored. The improved one-transistor cell is thus non-volatile, and additionally enjoys improved scalability, reliability, and performance.
Another one-transistor cell approach is disclosed in U.S. patent application Ser. No. 10/612,793, filed Jul. 2, 2003 by the present inventor, which is hereby incorporated by reference in its entirety. In this approach, a p-i-n diode is attached to one of the source/drain regions of the transistor, and the logic level of the cell is stored in the intrinsic region, which acts essentially as a dielectric. The p-i-n diode can be separately gated from the gating of the access transistor, and essentially functions as a negative-differential-resistance (NDR) device. However, this cell design is volatile and requires refreshing, thus limiting its utility.
Other NDR approaches have been proposed in the art using thyristors. For example, in Farid Nemati et al., “A Novel High-Density, Low Voltage SRAM Cell with a Vertical NDR Device,” 1998 Symp. on VLSI Tech. Digest of Technical Papers, § 7.3, pg. 66–67 (1998), and Farid Nemati et al., “A Novel Thyristor-Based SRAM Cell (T-RAM) for High Speed, Low-Voltage, Giga-Scale Memories,” IEDM, 11.5.1, pg. 283–286 (1999), (the “Nemati references”) both of which are hereby incorporated by reference in their entireties, it was suggested to use a negative-differential-resistance (NDR) vertical thyristor (a p-n-p-n device) in conjunction with an access transistor, yielding a cell design analogous in performance to an SRAM cell. The thyristor is gated during write operations to improve turn-on and turn-off speeds. Such a cell is SRAM-like in performance but DRAM-like in density. Again, however, the cell is volatile and requires refreshing.
In another thyristor approach disclosed in U.S. Published Patent Application 2004/0041212 (Ser. No. 10/232,855, filed Aug. 30, 2002) (the “'212 application”), which is hereby incorporated by reference in its entirety, a gated thyristor was used in a one-transistor cell. The thyristor couples to an epitaxially-raised source of the access transistor and is stacked over the access transistor, using metal-induced lateral crystallization techniques. Thus, in this thyristor-based approach, the thyristor is not formed exclusively in the substrate, and is in a sense partially lateral and partially vertical in nature. However, by forming portions of the thyristor laterally over the access transistor, a dense cell with faster performance can be fabricated. But such a cell is also relatively complicated to manufacture, and again is volatile and requires refreshing.
An exemplary schematic of the thyristor-based approaches referenced above (e.g., the Nemati reference and the '212 application) is shown in FIG. 1. The cell comprises an N-channel access transistor 118 whose n+ drain 121 is coupled to a bit line (BL) 112 and which is controlled by a first word line (WL1) 114. The access transistor 118 is serially coupled to a thyristor 120, which, because of its p-n-p-n structure, is drawn as two serially connected diodes. The n+ source 123 of the access transistor 118 comprises an end (cathode) of the thyristor 120, and comprises the storage node of the cell where a logic state ‘0’ or ‘1’ is stored, as will be explained later. The thyristor 120 is gated by a second word line (WL2) 116, which improves the switching speed of the cell. The other end (anode) of the thyristor 120, p+ region 125, is coupled to a reference voltage (Vref), which is set somewhere between the operating voltage of the device (Vcc; approximately 2.0 to 2.5 Volts) and ground (0 Volts), and which may be 1.0 Volts or so.
FIG. 2 represents conditions for writing and reading the cell of FIG. 1. When writing a logic ‘1’ state to the cell, both word lines 114 and 116 are turned on, and the bit line 112 stays low. The storage (cathode) node 123 assumes the bit line potential (low) while the p+ region (anode) 125 of the thyristor 120 remains at the reference voltage (Vref). This forward biases the thyristor 120, causing it to exceed its break over voltage (see FIG. 3), thus entering a highly conductive state. As a result, the potential of the storage node 123 is raised to nearly Vref and the junctions in the thyristor are saturated. Thereafter, when the first word line 114 is shut off, a charge remains on the storage node 123 equivalent to the raised potential, which represents a logic ‘1’ state. This charge can then be subsequently read by gating the first word line 114, and sensing the rise of potential on the bit line 112.
Writing a logic state ‘0’ implies the removal of all positive charges from the storage node 123 caused by earlier saturation. To write a logic ‘0’, and as shown in FIG. 2, first the bit line 112 is brought high, and a short time later the first word line 114 is brought high. Thereafter, the second word line 116 is gated, which significantly enhances the removal of any excess positive carriers previously stored. After the first word line 114 is shut off, the bit line 112 remains high for a short period, which ensures the removal of such positive carriers through the bit line 112 by strongly turning on transistor 118. As no charge is stored on the storage node 123 when in the logic ‘0’ state, no charge will flow to the bit line 112 when the ‘0’ is read by gating on the first word line 114. Accordingly, the potential on the floating bit line 112 remains unchanged, as shown in FIG. 2.
During standby, when the cell is neither read nor written to, the logic ‘0’ and ‘1’ data states are reflected in the I-V curve for the thyristor 120, as shown in FIG. 3. However, these data states are not perfectly stable. As noted earlier, when a logic ‘1’ is stored, a positive potential floats on storage node 123 by virtue that the junctions surrounding this node are reverse biased. However, with time, the positive potential on the storage node 123 will drop due to finite leakage mechanisms, e.g., thermal recombination of holes with electrons across depletion layer of the reverse biased junctions, as reflected in the arrow on FIG. 3. Such degradation in the logic ‘1’ data state will occur along a time scale on the order of tens of milliseconds. Similarly, the logic ‘0’ data state will also degrade. Specifically, the storage node 123, which is grounded when storing a ‘0,’ will slowly rise is potential due to radiation effects and/or ground noise transmissions along a time scale again on the order of tens of milliseconds.
The resulting effect is a reduction in margin between the logic ‘1’ and ‘0’ states, which affects the integrity of the data states and ultimately performance of the memory device. Accordingly, to ensure high performance, periodic refreshing may be required to ensure sufficient margin between the data states, as is the case with a standard DRAM cell. Moreover, this thyristor-based approach is volatile, as the stored data states would be lost when power is removed from the device. The degradation of the data states of such thyristor-based memory cells, the need to refresh them, and their volatility, are not optimal.
Accordingly, each of the aforementioned cells has drawbacks that hamper their utility. The art would be benefited from a cell design that had DRAM-type densities, SRAM-like performance (quick speed), is non-volatile, and which is reliable and relatively easy to manufacture. This disclosure presents such a solution.